Shirui Zhao

AI Hardware Architect | Probabilistic & Neuro-Symbolic Computing

I design energy-efficient hardware architectures for uncertainty-aware AI, bridging algorithm-architecture co-design for exact inference, sampling-based approximate inference, mixed-precision log-domain computation, and RISC-V-based programmable accelerators.

Selected Projects Publications

About Me

Shirui Zhao

I'm an AI hardware architect and researcher focusing on probabilistic machine learning and neuro-symbolic computing. My work targets scalable, energy-efficient processors for trustworthy and interpretable AI under uncertainty.

I'm currently a Postdoctoral Researcher at FACT lab, HKUST, advised by Prof. Yuan Xie.

Key highlights

  • Led 2x Intel 16nm chip tape-outs as chip architect
  • Published 14 papers (ISSCC, JSSC, CICC, DATE, FPT, TCAS-I)
  • Pioneered accelerators for sampling-based probabilistic ML (Knuth-Yao, Gumbel, log-domain)
  • Review: ISSCC, JSSC, TVLSI, TCAS-I/II

Research interests

Probabilistic AI Neuro-symbolic AI RISC-V / VLIW Exact & Approx. Inference Mixed-precision log-domain

Selected Research Projects

Intel 16nm Neuro-Symbolic AI Processor Architecture (EinChip)

Dec. 2024 - Present

KU Leuven | Role: Chip Architect & Design Lead

  • Designed an architecture integrating probabilistic ML and neural networks using mixed-precision log-domain datatypes.
  • Optimized dataflow mapping and accelerator design for high performance and energy efficiency.
  • Taped out in Intel 16nm (Mar. 2025); accepted by CICC'26.
Neuro-symbolic AI Mixed-precision Exact inference Tape-out

Energy-Efficient Datapath for Approximate Probabilistic Inference (MC2A)

May - Dec. 2024

KU Leuven | Role: Chip Architect & Design Lead

  • Designed a VLIW architecture for probabilistic workloads (PGM, combinatorial optimization, energy-based models).
  • Performed workload profiling and developed a roofline analysis model for sampling-based algorithms.
  • Implemented a parameterized architecture with a novel hardware Gumbel sampler; submitted to TVLSI.
Probabilistic AI MCMC Approx. inference

Intel 16nm Multi-core RISC-V with Probabilistic ISA (AIA)

Aug. 2020 - May 2024

KU Leuven | Role: Chip Architect & Design Lead

  • Designed and implemented a multi-core RISC-V architecture for probabilistic ML inference on edge devices.
  • Integrated a Knuth-Yao sampler and inter-core data sharing to improve performance and reduce memory footprint.
  • Completed Intel 16nm tape-out and published at ESSERC'24 and JSSC'25.
RISC-V Probabilistic ISA Tape-out

Neural Network Quantization & FPGA Acceleration

Apr. 2019 - May 2020

Southern University of Science and Technology

  • Developed a binarized neural network accelerator on FPGA for real-time scene text recognition; published at FPT'19 and IEEE Design & Test'20.
  • Researched mixed-precision processor design for quantized neural networks (published at DATE'21).
Binary NN FPGA Mixed-precision

Publications

Selected publications (from my Google Scholar profile).

Google Scholar

Journal Articles

LogSumExp: Efficient Approximate Logarithm Acceleration for Embedded Tractable Probabilistic Reasoning

Journal

L. Yao, Shirui Zhao, M. Trapp, J. Leslin, M. Verhelst and M. Andraud. IEEE Transactions on Circuits and Systems I: Regular Papers, 2025.

DOI

AIA: A Customized Multi-core RISC-V SoC for Discrete Sampling Workloads in 16 nm

Journal

Shirui Zhao, N. Shah, W. Meert and M. Verhelst. IEEE Journal of Solid-State Circuits, 2025.

DOI

DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm

Journal

N. Shah, L. I. G. Olascoaga, Shirui Zhao, W. Meert and M. Verhelst. IEEE Journal of Solid-State Circuits, 2022.

DOI

A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection

Journal

H. Lyu, F. An, Shirui Zhao, W. Mao and H. Yu. IEEE Design & Test, 2022.

DOI

Conference Papers

AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing

Conference

Shirui Zhao, N. Shah, W. Meert and M. Verhelst. IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.

DOI

TreeGRNG: Binary Tree Gaussian Random Number Generator for Efficient Probabilistic AI Hardware

Conference

J. Crols, G. Paim, Shirui Zhao and M. Verhelst. Design, Automation & Test in Europe (DATE), 2024.

DOI

Discrete Samplers for Approximate Inference in Probabilistic Machine Learning

Conference

Shirui Zhao, N. Shah, W. Meert and M. Verhelst. Design, Automation & Test in Europe (DATE), 2022.

DOI

A Reconfigurable Multiple-Precision Floating-Point MAC for High-Performance Computing

Conference

W. Mao, K. Li, X. Xie, Shirui Zhao, H. Li and H. Yu. Design, Automation & Test in Europe (DATE), 2021.

DOI

9.4 PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nm

Conference

N. Shah, L. I. G. Olascoaga, Shirui Zhao, W. Meert and M. Verhelst. IEEE International Solid-State Circuits Conference (ISSCC), 2021.

DOI

A 307-fps 351.7-GOPs/W Deep Learning FPGA Accelerator for Real-Time Scene Text Recognition

Conference

Shirui Zhao, F. An and H. Yu. International Conference on Field-Programmable Technology (FPT), 2019.

DOI

Preprints

(Add preprints here if you'd like – e.g., arXiv links.)

Curriculum Vitae

Education

Ph.D. in Electrical Engineering

KU Leuven, 2020

Thesis: "Hardware Design for Probabilistic Computing: Paving the Way to Efficient Artificial General Intelligence"

M.S. in Electrical Engineering

University of Chinese Academy of Sciences, 2015

B.S. in Electrical Engineering

Northwestern Polytechnic University, 2012

Contact

Get In Touch

Contact Information

Email

shiruizhao.pro@gmail.com

Office

FACT Lab, HKUST

Hong Kong

Office Hours

Monday & Wednesday: 2:00-4:00 PM

Or by appointment

Academic Profiles